//
//Data Component include file
//
//------------------------------------
// '-' Use Default
// '+' Change Initial
// '*' Change by mode
//------------------------------------
//extern CODE BYTE DataInit_Component_InitADC[];
//extern CODE BYTE DataInit_Component_InitScaler[];
//extern CODE BYTE DataInit_Component_Init1080p60_step1[];
//extern CODE BYTE DataInit_Component_Init1080p60_step2[];
//extern CODE BYTE DataInit_Component_Init1080p50_H56_step1[];
//extern CODE BYTE DataInit_Component_Init1080p50_H56_step2[];
//extern CODE BYTE DataInit_Component_Init1080i30_step1[];
//extern CODE BYTE DataInit_Component_Init1080i30_step2[];
//extern CODE BYTE DataInit_Component_Init1080i25_H28_step1[];
//extern CODE BYTE DataInit_Component_Init1080i25_H28_step2[];
//extern CODE BYTE DataInit_Component_Init1080i25_H31_step1[];
//extern CODE BYTE DataInit_Component_Init1080i25_H31_step2[];
//extern CODE BYTE DataInit_Component_Init720p60_step1[];
//extern CODE BYTE DataInit_Component_Init720p60_step2[];
//extern CODE BYTE DataInit_Component_Init720p50_step1[];
//extern CODE BYTE DataInit_Component_Init720p50_step2[];
//extern CODE BYTE DataInit_Component_Init576p_step1[];
//extern CODE BYTE DataInit_Component_Init576p_step2[];
//extern CODE BYTE DataInit_Component_Init576i_step1[];
//extern CODE BYTE DataInit_Component_Init576i_step2[];
//extern CODE BYTE DataInit_Component_Init480p_step1[];
//extern CODE BYTE DataInit_Component_Init480p_step2[];
//extern CODE BYTE DataInit_Component_Init480i_step1[];
//extern CODE BYTE DataInit_Component_Init480i_step2[];

	  
CODE BYTE DataInit_Component_Init1080p60_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01


//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x08,  //* Divider H
  0xC4, 0x97,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x0E,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xFF,0xFF
};

CODE BYTE DataInit_Component_Init1080p50_H56_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xF2,  //* VCO, Charge Pump
  0xC3, 0x0A,  //* Divider H
  0xC4, 0x4F,  //* Divider L
  0xC5, 0x03,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x0E,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  
  
  0xff,0xff
};


CODE BYTE DataInit_Component_Init1080i30_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x08,  //* Divider H
  0xC4, 0x97,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x18,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};


CODE BYTE DataInit_Component_Init1080i25_H28_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xF2,  //* VCO, Charge Pump
  0xC3, 0x0A,  //* Divider H
  0xC4, 0x4F,  //* Divider L
  0xC5, 0x0F,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x28,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};


CODE BYTE DataInit_Component_Init1080i25_H31_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xF2,  //* VCO, Charge Pump
  0xC3, 0x09,  //* Divider H
  0xC4, 0x47,  //* Divider L
  0xC5, 0x0F,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x28,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};

CODE BYTE DataInit_Component_Init720p60_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x06,  //* Divider H
  0xC4, 0x71,  //* Divider L
  0xC5, 0x09,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x26,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};

CODE BYTE DataInit_Component_Init720p50_step1[] = {
  0x00, 0x00,	//c 8a

//  0xFF, 0x00,
//  0x41, 0x3E,	

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x07,  //* Divider H
  0xC4, 0xBB,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x26,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};

CODE BYTE DataInit_Component_Init576p_step1[] = {
  0x00, 0x00,	//c 8a

//  0xFF, 0x00,
//  0x41, 0x3E,	

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x03,  //* Divider H
  0xC4, 0x5F,  //* Divider L
  0xC5, 0x0E,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x3A,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x37,  //* Bias
  0xE4, 0x14,  //* Bias
  0xE5, 0x42,  //* Bias
  0xE6, 0x20,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};


CODE BYTE DataInit_Component_Init576i_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x2E,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xC1,  //* VCO, Charge Pump
  0xC3, 0x03,  //* Divider H
  0xC4, 0x5F,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x80,  //*
  0xD2, 0x80,  //*
  0xD3, 0x80,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x80,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x37,  //* Bias
  0xE4, 0x14,  //* Bias
  0xE5, 0x42,  //* Bias
  0xE6, 0x20,  //* HS PGA
  0xE7, 0x2A,  //* AAF  
  0xE8, 0x2E,

  0xff,0xff
};

CODE BYTE DataInit_Component_Init480p_step1[] = {
  0x00, 0x00,	//c 8a

//  0xFF, 0x00,
//  0x41, 0x3E,	

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x03,  //* Divider H
  0xC4, 0x59,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x90,  //*
  0xD2, 0x90,  //*
  0xD3, 0x90,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x40,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x37,  //* Bias
  0xE4, 0x14,  //* Bias
  0xE5, 0x42,  //* Bias
  0xE6, 0x00,  //* Bias
  0xE7, 0x2A,  //* AAF  

  0xff,0xff
};


CODE BYTE DataInit_Component_Init480i_step1[] = {
  0x00, 0x00,	//c 8a

  0xFF, 0x01,  // Page 01

//0x02, 0x2a,  //+ Mux sel.
  0x05, 0x20,  //* AFE Mode, AAF on/off
//0x06, 0x00,  //+ Enable ADC

//----- LLPLL
//0xc0, 0x10,  //+ Input config.
  0xC2, 0xE2,  //* VCO, Charge Pump
  0xC3, 0x03,  //* Divider H
  0xC4, 0x59,  //* Divider L
  0xC5, 0x00,  //* Phase
//0xc6, 0x20,  //+ Loop Filter 0, Change to 7 later...
//0xc7, 0x04,  //- VCO Norminal freq.
//0xc8, 0x00,  //- VCO Norminal freq.
//0xc9, 0x00,  //+ Pre Coast
//0xca, 0x00,  //+ Post Coast
//0xcb, 0xce,  //+ Power, SOG Threshold
//0xcc, 0x02,  //+ Sync Output sel.
//0xcd, 0x54,  //. Charge Pump Fine Control
//----- ADC Gain
  0xD0, 0x07,  //*
  0xD1, 0x10,  //*
  0xD2, 0x10,  //*
  0xD3, 0x10,  //*
//----- Clamp
//0xd4, 0x00,  //+ Mode
//0xd5, 0x00,  //+ Start
//0xd6, 0x10,  //+ Stop
  0xD7, 0x80,  //* Master Location
//0xd8, 0x00,  //- Debug off
//0xd9, 0x01,  //+ G Level
//0xda, 0x80,  //+ B Level
//0xdb, 0x80,  //+ R Level
//----- LLPLL Misc.
//0xdc, 0x10,  //+ HS width
//0xe0, 0x00,  //- Test
//0xe1, 0x05,  //+ GPLL Pd.
//----- AFE
  0xE2, 0x59,  //* Bais, VREF
  0xE3, 0x17,  //* Bias
  0xE4, 0x34,  //* Bias
  0xE5, 0x33,  //* Bias
  0xE6, 0x20,  //* HS PGA
  0xE7, 0x2A,  //* AAF  
  0xE8, 0x2E,

  0xFF,0xFF
};

